The present invention relates to integrated circuit design, and more specifically, to the buffer-bay placement in an integrated circuit.
An integrated circuit, such as a microprocessor, for example, is a collection of electronic circuits that are also referred to as a chip. Integrated circuit design involves several phases. In a logic design phase, transistors and other components (e.g., buffers, capacitors) that must be interconnected to fulfill the desired functionality of the integrated circuit are determined. In the physical synthesis phase, the placement of the components is determined. In addition to functionality, timing requirements are established for the final integrated circuit such that the chip must perform the specified functionality within a specified duration of time. In order to meet the timing requirements, timing analysis is performed at different phases of the design, and the design is modified to address components deemed responsible for the failure to meet timing requirements. An exemplary integrated circuit can include many components (e.g., over ten billion transistors). Integrated circuit design may be performed hierarchically with lower-level functions grouped as macros, which can also be referred to as child blocks relative to larger-scale parent blocks. For longer signal paths through an integrated circuit, repeaters or buffers are used to strengthen the signal. Design integrators can reserve space within child blocks for buffer placement, where the reserved space is referred to as buffer-bays. The buffer-bays can be utilized by design integrators but may be a hindrance to designers who must design around the buffer-bays, which may result in increased resource utilization, particularly in congested areas of an integrated circuit design.